LinuxでL1、L2、L3キャッシュ、RAMのサイズを知る方法はありますか？ [閉鎖]

すでにlshwインストールしている場合：

$ sudo lshw -C memory

はい

$ sudo lshw -C memory
...
  *-cache:0
       description: L1 cache
       physical id: a
       slot: Internal L1 Cache
       size: 32KiB
       capacity: 32KiB
       capabilities: asynchronous internal write-through data
  *-cache:1
       description: L2 cache
       physical id: b
       slot: Internal L2 Cache
       size: 256KiB
       capacity: 256KiB
       capabilities: burst internal write-through unified
  *-cache:2
       description: L3 cache
       physical id: c
       slot: Internal L3 Cache
       size: 3MiB
       capacity: 8MiB
       capabilities: burst internal write-back
  *-memory
       description: System Memory
       physical id: 2a
       slot: System board or motherboard
       size: 8GiB
     *-bank:0
          description: SODIMM DDR3 Synchronous 1334 MHz (0.7 ns)
          product: M471B5273CH0-CH9
          vendor: Samsung
          physical id: 0
          serial: 67010644
          slot: DIMM 1
          size: 4GiB
          width: 64 bits
          clock: 1334MHz (0.7ns)
     *-bank:1
          description: SODIMM DDR3 Synchronous 1334 MHz (0.7 ns)
          product: 16JTF51264HZ-1G4H1
          vendor: Micron Technology
          physical id: 1
          serial: 3749C127
          slot: DIMM 2
          size: 4GiB
          width: 64 bits
          clock: 1334MHz (0.7ns)

プロセッサ

サイズだけに興味があるなら。lscpuから始めましょうutil-linux。

はい

$ lscpu
Architecture:          x86_64
CPU op-mode(s):        32-bit, 64-bit
Byte Order:            Little Endian
CPU(s):                4
On-line CPU(s) list:   0-3
Thread(s) per core:    2
Core(s) per socket:    2
Socket(s):             1
NUMA node(s):          1
Vendor ID:             GenuineIntel
CPU family:            6
Model:                 37
Model name:            Intel(R) Core(TM) i5 CPU       M 560  @ 2.67GHz
Stepping:              5
CPU MHz:               1199.000
BogoMIPS:              5319.88
Virtualization:        VT-x
L1d cache:             32K
L1i cache:             32K
L2 cache:              256K
L3 cache:              3072K
NUMA node0 CPU(s):     0-3

x86情報

x86infoというパッケージ/コマンドも必要です。 i386/x86_64 があると仮定すると、x86info -cキャッシュに関する詳細情報を提供する必要があります。

はい

$ x86info -c
x86info v1.30.  Dave Jones 2001-2011
Feedback to <[email protected]>.

Found 4 identical CPUs
Extended Family: 0 Extended Model: 2 Family: 6 Model: 37 Stepping: 5
Type: 0 (Original OEM)
CPU Model (x86info's best guess): Core i7 (Nehalem) [Clarkdale/Arrandale]
Processor name string (BIOS programmed): Intel(R) Core(TM) i5 CPU       M 560  @ 2.67GHz

Cache info
 L1 Instruction cache: 32KB, 4-way associative. 64 byte line size.
 L1 Data cache: 32KB, 8-way associative. 64 byte line size.
 L2 (MLC): 256KB, 8-way associative. 64 byte line size.
TLB info
 Instruction TLB: 2MB or 4MB pages, fully associative, 7 entries
 Instruction TLB: 4K pages, 4-way associative, 64 entries.
 Data TLB: 4KB or 4MB pages, fully associative, 32 entries.
 Data TLB: 4KB pages, 4-way associative, 64 entries
 Data TLB: 4K pages, 4-way associative, 512 entries.
 Data TLB: 4KB or 4MB pages, fully associative, 32 entries.
 Data TLB: 4KB pages, 4-way associative, 64 entries
 64 byte prefetching.
 Data TLB: 4K pages, 4-way associative, 512 entries.
Found unknown cache descriptors: dd 
Total processor threads: 4
This system has 1 dual-core processor with hyper-threading (2 threads per core) running at an estimated 2.65GHz

getconf

getconf -a | grep CACHE

以下を提供します。

LEVEL1_ICACHE_SIZE                 32768
LEVEL1_ICACHE_ASSOC                8
LEVEL1_ICACHE_LINESIZE             64
LEVEL1_DCACHE_SIZE                 32768
LEVEL1_DCACHE_ASSOC                8
LEVEL1_DCACHE_LINESIZE             64
LEVEL2_CACHE_SIZE                  262144
LEVEL2_CACHE_ASSOC                 8
LEVEL2_CACHE_LINESIZE              64
LEVEL3_CACHE_SIZE                  20971520
LEVEL3_CACHE_ASSOC                 20
LEVEL3_CACHE_LINESIZE              64
LEVEL4_CACHE_SIZE                  0
LEVEL4_CACHE_ASSOC                 0
LEVEL4_CACHE_LINESIZE              0

または単一レベルの場合：

getconf LEVEL2_CACHE_SIZE

このインターフェイスの素晴らしい点は、POSIX C関数を囲むラッパーにすぎないため、sysconf（キャッシュパラメータはPOSIXではなく拡張です）Cコードでも使用できることです。

long l2 = sysconf(_SC_LEVEL2_CACHE_SIZE);

Ubuntu 16.04でテストされました。

x86 CPUIDコマンド

CPUID x86コマンドはキャッシュ情報も提供し、ユーザーモードで直接アクセスできます。https://en.wikipedia.org/wiki/CPUID

glibcはx86でこの方法を使用しているようです。ステップデバッグ/コマンドトレースでは確認しませんでしたが、2.28のソースコードはsysdeps/x86/cacheinfo.cこの方法：

__cpuid (2, eax, ebx, ecx, edx);

TODO 最小限の C 例を作成します。今はあまりにも怠惰です。次のことについて質問します。https://stackoverflow.com/questions/14283171/how-to-receive-l1-l2-l3-cache-size-using-cpuid-instruction-in-x86

ARMには、キャッシュサイズIDレジスタ（CCSIDR）などのレジスタを介してキャッシュサイズを見つけるアーキテクチャ定義メカニズムもあります。ARMv8プログラママニュアル11.6「キャッシュ検索」の概要。

メモリサイズ

さまざまな方法：

free
cat /proc/meminfo
sysinfo()

サージ：

• https://stackoverflow.com/questions/20348007/how-can-i-find-out-the-total-physical-memory-ram-of-my-linux-box-suitable-to-b
• https://askubuntu.com/questions/898941/how-to-check-ram-size/898942
• https://stackoverflow.com/questions/349889/how-do-you-define-the-amount-of-linux-system-ram-in-c

sysfs2008年以来、/sys Linuxファイルシステムにエクスポートされたいくつかの特殊ファイルがあります。

https://www.kernel.org/doc/Documentation/ABI/testing/sysfs-devices-system-cpu

What:       /sys/devices/system/cpu/cpu*/cache/index*/<set_of_attributes_mentioned_below>
Date:       July 2014(documented, existed before August 2008)
Description:    Parameters for the CPU cache attributes

    allocation_policy:
        - WriteAllocate: allocate a memory location to a cache line
                 on a cache miss because of a write
        - ReadAllocate: allocate a memory location to a cache line
                on a cache miss because of a read
        - ReadWriteAllocate: both writeallocate and readallocate

    coherency_line_size: the minimum amount of data in bytes that gets
                 transferred from memory to cache

    level: the cache hierarchy in the multi-level cache configuration

    number_of_sets: total number of sets in the cache, a set is a
            collection of cache lines with the same cache index

    physical_line_partition: number of physical cache line per cache tag

    shared_cpu_list: the list of logical cpus sharing the cache

    shared_cpu_map: logical cpu mask containing the list of cpus sharing
            the cache

    size: the total cache size in kB

    type:
        - Instruction: cache that only holds instructions
        - Data: cache that only caches data
        - Unified: cache that holds both data and instructions

    ways_of_associativity: degree of freedom in placing a particular block
                of memory in the cache

    write_policy:
        - WriteThrough: data is written to both the cache line
                and to the block in the lower-level memory
        - WriteBack: data is written only to the cache line and
                 the modified cache line is written to main
                 memory only when it is replaced

身分証明書：

What:       /sys/devices/system/cpu/cpu*/cache/index*/id
Date:       September 2016
Contact:    Linux kernel mailing list <[email protected]>
Description:    Cache id

    The id provides a unique number for a specific instance of
    a cache of a particular type. E.g. there may be a level
    3 unified cache on each socket in a server and we may
    assign them ids 0, 1, 2, ...

    Note that id value can be non-contiguous. E.g. level 1
    caches typically exist per core, but there may not be a
    power of two cores on a socket, so these caches may be
    numbered 0, 1, 2, 3, 4, 5, 8, 9, 10, ...